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HT82J30R/HT82J30A 16 Channel A/D MCU with SPI Interface
Technical Document
* Tools Information * FAQs * Application Note
Features
* Operating voltage: * 6-level subroutine nesting * 16 channel 8-bit resolution A/D converter * 1 channel (6+2)-bit PWM output shared with an I/O
fSYS=4MHz: 2.2V~5.5V crystal clock mode
* fSYS=12MHz: 2.7V~3.7V RC clock mode * 35 bidirectional I/O lines (max.) * 2 interrupt inputs shared with I/O lines * 8-bit programmable timer/event counter with overflow
line
* Bit manipulation instruction * 15-bit table read instruction * 63 powerful instructions * LVR reset voltage of 3V0.3V * All instructions executed in one or two machine
interrupt and 7-stage prescaler
* On-chip crystal and RC oscillator * Watchdog Timer * 409615 program memory ROM * 2168 data memory RAM * PFD function for sound generation * HALT function and wake-up feature reduces power
cycles
* PB2, PB3, PD4, PD7 can be optioned as either
CMOS or NMOS outputs
* Integrated dual SPI interfaces * 28-pin SKDIP/SOP and 44-pin QFP packages
consumption
* Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
General Description
The HT82J30R/HT82J30A are 8-bit high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The mask version HT82J30A is fully pin and functionally compatible with the OTP version HT82J30R device. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, Watchdog timer, SPI interfaces, Power Down and wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. With the provision of dual SPI interfaces the devices are especially suitable for Joystick Encoder applications. The HT82J30A is under development and will be available soon.
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HT82J30R/HT82J30A
Block Diagram
P A 5 /IN T 0 , P A 6 /IN T 1
In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C
TM RC TM R P A 3 /P F D M U X PA4 M U X PD0 PD1 PD2 PD3 PD4 PD5 PD7 PF0 PF1 PF2 fS /4 P r e s c a le r P A 4 /T M R fS
YS
WDT In s tr u c tio n R e g is te r MP M U X D a ta M e m o ry
YS
W DT OSC /P W /S C /S C /S D /S D ~P /S D /S D /S C /S C M S_A K_A I_ A O _A D6 O _B I_ B K_B S_B
PW M PDC PD PO R T D ,F
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX PCC STATUS PA3,PA5 PC 1 6 -C h a n n e l A /D C o n v e rte r PBC PORT B PB PORT C
P C 0 /A N 8 ~ P C 7 /A N 1 5
S h ifte r
P B 0 /A N 0 ~ P B 7 /A N 7 PA0 PA3 PA4 PA5 PA6 PA7 ~P /P /T /IN /IN A2 FD MR T0 T1
OSC2
OS RE VD VS
C1 S D S
ACC
LVR
PAC PA
PORT A
Pin Assignment
P F 2 /S C S P F 1 /S C K P F 0 /S D P D 7 /S D O P B 7 /A P B 6 /A P B 5 /A P B 4 /A P C 7 /A N P C 6 /A N P A 3 /P
P F 0 /S D I_ B 1 2 3 4 5 6 7 8 9 P D 7 /S D O _ B P A 3 /P F D PA2 PA1 PA0 PB3 PB2 PB1 AVDD & VREF VSS PB0 PC2 PC1
28 27 26 25 24 23 22 21 20 10 11 12 13 14 19 18 17 16 15
P F 1 /S C K _ B P F 2 /S C S _ B P A 4 /T M R P A 5 /IN T 0 P A 6 /IN T 1 PA7 OSC2 OSC1 VDD RES PD1 PD2 PD3 PD4 PB PC5 PB PB PB PA PA PA 3 /A N 2 /A N 1 /A N VRE AVD AVS 0 /A N /A N 1 D S 0 3 9 10 11 2 1 0 3 2 1 F 8 7 6 5 4 3 2 1
_B _B I_ B _B N7 N6 N5 N4 15 14 FD 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 H T 8 2 J 3 0 R /H T 8 2 J 3 0 A 4 4 Q F P -A 29 28 27 26 25 24 12 13 14 15 16 17 18 19 20 21 22 23 NC PA PA PA PA PD PD 7 5 6 4 /T M R 5 /IN T 0 6 /IN T 1 OSC2 OSC1 VDD VSS
H T 8 2 J 3 0 R /H T 8 2 J 3 0 A 2 8 S K D IP -A /S O P -A
RE PD PD PD PD PD PC PC PC PC PC S 0 /P 1 /S 2 /S 3 /S 4 /S 0 /A 1 /A 2 /A 3 /A 4 /A WM0 CS_A CK_A D I_ A DO _A N8 N9 N10 N11 N12
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HT82J30R/HT82J30A
Pin Description
Pin Name PA0~PA2 PA3/PFD PA4/TMR PA5/INT0 PA6/INT1 PA7 I/O Options Description
I/O
Bidirectional 8-bit input/output port. Each individual pin on this port can be configPull-high* ured as a wake-up input by a configuration option. Software instructions deterWake-up mine if the pin is a CMOS output or Schmitt trigger input. Configuration options PA3 or PFD determine which pin on this port have pull-high resistors. The PFD, TMR and external interrupt input are pin-shared with PA3, PA4, and PA5 , PA6, respectively. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pin on this port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions Once selected as an A/D input, the I/O function and pull-high resistor functions are disable automatically. PB2, PB3 has CMOS or NMOS output option. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pin on this port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions Once selected as an A/D input, the I/O function and pull-high resistor functions are disabled automatically.
PB0/AN0~ PB7/AN7
I/O
Pull-high*
PC0/AN8~ PC7/AN15
I/O
Pull-high*
PD0/PWM0 PD1/SCS_A PD2/SCK_A PD3/SDI_A PD4/SDO_A PD5~PD6 PD7/SDO_B PF0/SDI_B PF1/SCK_B PF2/SCS_B
Bi-directional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pin on this port have pull-high resistors. PD0 is pin-shared with the PWM output sePull-high* I/O lected via configuration option. PD0 or PWM PD1~PD4 are pin-shared with SPI interface A. PD4, PD7 have CMOS or NMOS output options. PD7 is pin-shared with the SPI interface B. Bidirectional 3-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pin on this port have pull-high resistors. PF0~PF2 is pin-shared with the SPI interface B. OSC1 and OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock is selected, pin OSC2 can be used to measure the system clock at 1/4 system frequency. Schmitt trigger reset input. Active low Positive power supply Negative power supply, ground Analog positive power supply Analog negative power supply 8-bit A/D reference voltage input pin
I/O
Pull-high*
OSC1 OSC2 RES VDD VSS AVDD AVSS VREF
I O I 3/4 3/4 3/4 3/4 3/4
Crystal or RC 3/4 3/4 3/4 3/4 3/4 3/4
Note: * The pull-high resistors of each I/O port are controlled by options.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Storage Temperature ............................-50C to 125C Operating Temperature...............................0C to 70C IOH Total............................................................-100mA
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HT82J30R/HT82J30A
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 VDD Operating Voltage 3/4 3V 5V 3V No load, system HALT 5V 3V No load, system HALT 5V 3/4 3/4 3/4 3/4 3/4 3V I/O Port Sink Current 5V IOH 3V I/O Port Source Current 5V RPH VAD EAD 3V Pull-high Resistance 5V A/D Input Voltage A/D Conversion Error 5V IADC 3V Only ADC Enable, Others Disable 5V No load 3/4 3V 3/4 3/4 3/4 3/4 3/4 VOH=0.9VDD 3/4 3/4 3/4 3/4 Configuration option: 3V VOL=0.1VDD Conditions fSYS=4MHz fSYS=12MHz at 56kW RC mode No load, fSYS=12MHz ADC disable Min. 2.2 2.7 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 3/4 4 10 -2 -5 20 10 0 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 1 4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 8 20 -4 -10 60 30 3/4 0.5 0.5 0.5 1.5 Max. 5.5 3.7 2 6 5 10 1 2 0.3VDD VDD 0.4VDD VDD 2.1 3/4 3/4 3/4 3/4 100 50 VDD 1 1 1 3 Ta=25C Unit V V mA mA mA mA mA mA V V V V V mA mA mA mA kW kW V LSB LSB mA mA
IDD
Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset
ISTB1
ISTB2
VIL1 VIH1 VIL2 VIH2 VLVR IOL
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HT82J30R/HT82J30A
A.C. Characteristics
Symbol Parameter System Clock (Crystal OSC) System Clock (RC OSC) Timer I/P Frequency (TMR) Test Conditions VDD 3/4 3/4 3/4 3/4 3/4 3/4 3V 5V tWDT1 tWDT2 tRES tSST tINT tAD tADC tADCS tCS_SK tSPICK Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (System Clock) External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sample Time SPI SCS to SCK Time SPI Clock Time 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~2.6V 2.7V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 3/4 3/4 Min. 400 400 1000 1000 0 0 45 32 215 217 1 3/4 1 1 3/4 3/4 50 400 Typ. 3/4 3/4 3/4 12000 3/4 3/4 90 65 3/4 3/4 3/4 1024 3/4 3/4 76 32 3/4 3/4 Max. 4000 8000 4000 14000 4000 8000 180 130 216 218 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Ta=25C Unit kHz kHz kHz kHz kHz kHz ms ms tWDTOSC *tSYS ms tSYS ms ms tAD tAD ns ns
fSYS1
fSYS2
fTIMER
tWDTOSC Watchdog Oscillator Period
Note: *tSYS= 1/fSYS1 or 1/fSYS2
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HT82J30R/HT82J30A
Functional Description
Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter controls the sequence in which the instructions stored in the program memory are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
T1 T2 T3 T4 T1 T2
incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, a conditional skip execution, loading the PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt or a return from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise the program proceeds with the next instruction. The lower byte of the program counter is a readable and writeable register. Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
S y s te m
C lo c k
T3
T4
T1
T2
T3
T4
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 1 0 0 1 1 *3 0 0 1 1 1 0 0 *2 0 1 0 0 1 0 1 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Mode Initial Reset INT0 External Interrupt INT1 External Interrupt Timer/Event Counter Overflow Reserved SPI_A Interrupt SPI_B Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter+2 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.00 6 S11~S0: Stack register bits @7~@0: PCL bits December 20, 2006
HT82J30R/HT82J30A
Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 4K15 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H * Location 00CH
This location is reserved for the A/D converter interrupt service program. If the interrupt is activated, when the A/D conversion is completed, if the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Location 010H
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
* Location 004H
Location 010H is reserved for when 8 bits of data have been received or transmitted successfully from serial interface A. When the related interrupts are enabled, and the stack is not full, the program begins execution at location 010H.
* Location 014H
This area is reserved for the external interrupt service program. If the INT0 input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
Location 014H is reserved for when 8 bits of data have been received or transmitted successfully from serial interface B. When the related interrupts are enabled, and the stack is not full, the program begins execution at location 014H.
* Location 018H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
000H 004H 008H 00CH 010H 014H 018H D e v ic e In itia liz a tio n P r o g r a m IN T 0 E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e A /D C o n v e r te r In te r r r u p t S u b r o u tin e S P I_ A In te r r u p t S u b r o u tin e S P I_ B In te r r u p t S u b r o u tin e IN T 1 E x te r n a l In te r r u p t S u b r o u tin e P ro g ra m M e m o ry
This location is reserved for the external interrupt service program. If the INT1 input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at this location.
* Table location
n00H nFFH
L o o k - u p T a b le ( 2 5 6 W o r d s )
FFFH
L o o k - u p T a b le ( 2 5 6 W o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to F
Program Memory Instruction TABRDC [m] TABRDL [m]
Any location in the Program Memory space can be used as a look-up table. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfers the contents of the lower-order byte to the specified data memory, and the higher-order byte to the TBLH register. Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH. Any unused bits are read as 0. The Table Higher-order byte register, TBLH, is read only. The table pointer, TBLP, is a read/write register, which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH register is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of TBLH in the main routine are likely to be changed by the table read instruction used in the ISR and errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table Table Location
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.00 7 December 20, 2006 P11~P8: Current program counter bits
HT82J30R/HT82J30A
read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It should not be enabled until TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost as only the most recent 6 return addresses are stored. Data Memory - RAM The data memory is designed with 2268 bits. The data memory is divided into 2 functional groups: special function registers and general purpose data memory. Most of them are read/write, but some are read only. Reading any unused locations will return the result 00H. The general purpose data memory, addressed from 28H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the memory pointer registers MP. Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data memory pointed to by MP. Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H ADR ADCR ACSR SBCR_A SBDR_A SBCR_B SBDR_B G e n e ra l P u rp o s e D a ta M e m o ry (2 1 6 B y te s ) :U nused R e a d a s "0 0 " PF PFC IN T C 1 PA PAC PB PBC PC PCC PD PDC PW M S p e c ia l P u r p o s e D a ta M e m o ry TM R TM RC STATUS IN T C ACC PCL TBLP TBLH In d ir e c t A d d r e s s in g R e g is te r MP
FFH
RAM Mapping Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
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HT82J30R/HT82J30A
* Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
converter end-of-conversion interrupt and two SPI interrupts. The interrupt control registers INTC and INTC1 both contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked by clearing the EMI bit. This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flags are recorded. If a certain interrupt requires servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of INTC or INTC1 to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decreased. If immediate service is desired, the stack has to be prevented from becoming full. All interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which corrupts the desired control sequence, the programmer should save these contents first. External interrupts are triggered by a high to low transition on pins INT0 or INT1 which will in turn set the related interrupt request flag, which is bit 4 of INTC or bit 6 of INTC1. When the respective interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 004H or 018H will occur. The external interrupt request flag and EMI bits will cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (bit 5 of INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the timer/event Function
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flags. In addition, operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The microcontroller provides two external interrupts, an internal timer/event counter overflow interrupt, an A/D Bit No. 0 Label C
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
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Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI_A ETI EADI EIF_A TF ADF 3/4 Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt (1= enabled; 0= disabled) Controls the Timer/Event Counter interrupt (1= enabled; 0= disabled) Controls the A/D converter interrupt (1= enabled; 0= disabled) External interrupt request flag (1= active; 0= inactive) Internal Timer/Event Counter request flag (1= active; 0= inactive) End of A/D conversion interrupt request flag (1= active; 0= inactive) Unused bit, read as 0 INTC (0BH) Register Bit No. 0 1 2 3, 7 4 5 6 Label ESII_A ESII_B EEI_B 3/4 SIF_A SIF_B EIF_B Function Controls the serial interface interrupt (1= enabled; 0= disabled) Controls the serial interface interrupt (1= enabled; 0= disabled) Controls the INT1 external interrupt (1= enabled; 0= disabled) Unused bits, read as 0 Serial interface interrupt request flag (1= active; 0= inactive) Serial interface interrupt request flag (1= active; 0= inactive) INT1 External interrupt request flag (1= active; 0= inactive) INTC1 (1EH) Register counter interrupt request flag is set, a subroutine call to location 00CH will occur. The related interrupt request flag will be reset and the EMI bit cleared to disable further interrupts. The A/D converter end-of-conversion interrupt is initialized by setting the A/D end-of-conversion interrupt request flag (bit 6 of INTC), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the end of A/D conversion interrupt request flag is set, a subroutine call to location 0CH will occur. The related interrupt request flag will be reset and the EMI bit cleared to disable further interrupts. There are two serial interface interrupts, which will be generated when the interface receives or transmits 8-bits of data. These interrupts are indicated by the interrupt flags, SIF_A; bit 4 of INTC1, and SIF_B; bit 5 of INTC1. The serial interface interrupts are enabled by setting the serial interface interrupt control bits, ESII_A; bit 0 of INTC1 and ESII_B; bit 1 of INTC1. After the res p e c t iv e i n t e r f ac e i s e n a b l ed by s et t i n g t h e corresponding SBEN bit, which is bit 4 of either SBCR_A or SBCR_B, if the stack is not full and the corresponding SIF_A or SIF_B bit is set, a subroutine call to location 10H or 14H occurs. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bits are set to 1 (if the stack is not full). To return from the interrupt subroutine, a RET or RETI instruction may be executed. RETI will set the EMI bit to enable further interrupts, but RET will not. Interrupts, occurring in the interval between rising edge of two consecutive T2 pulses, will be serviced on the later of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the priorities in the follow table apply. These can be masked by clearing the EMI bit. Interrupt Source INT0 External Interrupt Timer/Event Counter Overflow End of A/D Conversion Interrupt SPI_A Interrupt SPI_B Interrupt INT1 External Interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request flag (ADF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI) and enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EEI, ETI, EADI are used to control the enabling/disabling of interrupts. These bits
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prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, EIF, ADF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged if a CALL instruction is executed in the interrupt subroutine. Oscillator configuration There are 2 oscillator circuits in the microcontroller.
V C1 R OSC1
OSC DD
and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works within a period of 65ms at 5V. The WDT oscillator can be disabled by options to conserve power. Watchdog Timer - WDT The clock source of WDT is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), chosen via a configuration option. This timer is designed to prevent software malfunctions or the program jumping to unknown locations. The Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. If the internal oscillator, which is an RC oscillator with a nominal period of 65ms at 5V, is selected, it is first divided by 32768~65536 to get a time-out period of approximately 2.1s~4.3s. This time-out period may vary with temperature, VDD and process variations. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT instruction will stop the system clock. The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. But in the Power-down mode, the overflow will initialize a warm reset, and only the program counter and the SP are reset to zero. To clear the contents of the WDT, three methods are adopted; an external reset (a low level on the RES pin), a software instruction or a HALT instruction. The software instructions include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the configuration option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of a time-out.
OSC1
C2 R1 OSC2 C r y s ta l O s c illa to r fS Y S /4 N M O S o p e n d r a in OSC2 RC O s c illa to r
System Oscillator Both of them are designed for system clocks, namely the external RC oscillator, the external Crystal oscillator and the internal RC oscillator, the choice of which is determined by configuration options. The Power Down mode stops the system oscillator to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VDD is required and the resistance must range from 47kW to 750kW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the oscillation frequency may vary with VDD, temperature and process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to obtain a frequency reference, but two external capacitors connected between OSC1 and OSC2 and ground are required. The WDT oscillator is a free running on-chip RC oscillator,
S y s te m C lo c k /4 O p tio n S e le c t W DT OSC fS 8 - b it C o u n te r
7 - b it C o u n te r
T
T
W D T T im e - o u t fS /2 15~ fS /2 16 CLR W DT
Watchdog Timer Rev. 1.00 11 December 20, 2006
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Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following...
* The system oscillator will be turned off but the WDT
To minimize power consumption, all the I/O pins should be carefully managed before entering the Power-down mode. Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
oscillator remains running (if the WDT oscillator is selected).
* The contents of the on chip RAM and registers remain
unchanged.
* The WDT and WDT prescaler will be cleared and re-
sume counting again (if the WDT clock comes from the WDT oscillator).
* All of the I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared.
The system can leave the Power-down mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for chip reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP; the others remain in their original status. The port A wake-up and interrupt methods of wake-up can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device using configuration options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power-down mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period has finished.
The WDT time-out during Power-down is different from other chip reset conditions, since it can perform a warm reset that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the Power-down mode. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from Power-down will enable the SST delay. An extra option load time delay is added during a system reset (power-up, WDT time-out at normal mode or RES reset).
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The functional unit chip reset status is shown below. Program Counter Interrupt Prescaler WDT Timer/Event Counter Input/Output Ports Stack Pointer
V
DD
VDD RES S S T T im e - o u t C h ip R eset tS
ST
000H Disable Clear Clear. After a master reset, WDT begins counting Off Input mode Points to the top of the stack
RES
0 .0 1 m F *
Reset Timing Chart
HALT W DT
W a rm
R eset
100kW RES 10kW 0 .1 m F *
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Configuration Reset Circuit
Note:
* Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
The register states is summarized in the table. Register MP ACC Program Counter TBLP TBLH STATUS INTC INTC1 WDTS PA PAC PB PBC PC PCC PD PDC PF Reset (Power-on) xxxx xxxx xxxx xxxx 000H xxxx xxxx -xxx xxxx --00 xxxx -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu --1u uuuu -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu --uu uuuu -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 RES Reset (HALT) uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu --01 uuuu -000 0000 -000 -000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- -111 WDT Time-out (HALT)* uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --- -uuu
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Register PFC INTC1 PWM ADR ADCR ACSR SBCR_A SBDR_A SBCR_B SBDR_B Note: Reset (Power-on) ---- -111 -000 0000 xxxx xxxx xxxx xxxx 0100 0000 1--- --00 0110 0000 xxxx xxxx 0110 0000 xxxx xxxx WDT Time-out RES Reset (Normal Operation) (Normal Operation) ---- -111 -000 0000 xxxx xxxx xxxx xxxx 0100 0000 1--- --00 0110 0000 xxxx xxxx 0110 0000 xxxx xxxx ---- -111 -000 0000 xxxx xxxx xxxx xxxx 0100 0000 1--- --00 0110 0000 xxxx xxxx 0110 0000 xxxx xxxx RES Reset (HALT) ---- -111 -000 0000 xxxx xxxx xxxx xxxx 0100 0000 1--- --00 0110 0000 xxxx xxxx 0110 0000 xxxx xxxx WDT Time-out (HALT)* --- -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
* stands for warm reset u stands for unchanged x stands for unknown
Timer/Event Counter A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter whose clock may come from an external source or the system clock. Using an external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. The timer/event counter can generate PFD signal by using an external or internal clock. The PFD frequency is determined by the equation fINT/[2(256-N)]. There are 2 registers related to the timer/event counter; TMR and TMRC. Two physical registers are mapped to the TMR location; writing to TMR places the start value into the timer/event counter preload register. Reading TMR retrieves the contents of the timer/event counter. The TMRC register is a timer/event counter control register, which defines some options. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from the external TMR pin. The timer mode functions as a normal timer with the clock source coming from the fINT clock. The pulse width measurement mode can be used to measure a high or low level duration of the external TMR pin. The counting is based on fINT. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates an interrupt request flag (TF; bit 5 of INTC) at the same time.
In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR pin has received a transient from low to high (or high to low if the TE bit is 0) it will start counting until the TMR pin returns to its original level and resets the TON bit. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only a one cycle measurement can be implemented. Until the TON bit is again set, the cycle measurement will not function even if it receives further transient pulses. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of a counter overflow, the counter is reloaded from the timer/event counter preload register and issues an interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON bit will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON bit can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt service. In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until an overflow occurs. When the timer/event counter is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the programmer.
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The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The overflow signal of the timer/event counter can be used to generate the PFD signal. Input/Output Ports There are 35 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC, PD and PF, which are mapped to the data memory of [12H], [14H], [16H], [18H] and [22H] respectively. All of these I/O ports can be used for input and output operations. For input Bit No. Label operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H or 22H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC, PFC) to control the input/output configuration. With this control register, a CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must Function Defines the prescaler stages, PSC2, PSC1, PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR active edge of the timer/event counter: In Event Counter Mode (TM1,TM0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (TM1,TM0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable or disable the timer counting (0=disable; 1=enable) Unused bits, read as 0 Defines the operating mode (TM1, TM0)= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC (0EH) Register
0 1 2
PSC0 PSC1 PSC2
3
TE
4 5
TON 3/4
6 7
TM0 TM1
PW M (6 + 2 ) C o m p a re fS
YS
T o P D 0 C ir c u it
8 - s ta g e P r e s c a le r 8 -1 M U X PSC2~PSC0 TM R TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r 1 /2 O v e r flo w to In te rru p t PFD f IN
T
D a ta B u s TM 1 TM 0 8 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
Timer/Event Counter
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write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, all I/Os except PB2, PB3, PD2, PD7 are CMOS types. There are options to define PB2, PB3, PD2, PD7 as either CMOS or NMOS types. These control registers are mapped to locations 13H, 15H, 17H,19H and 23H. After a device reset, these input/output lines remain at high levels or a floating state, depending upon the pull-high configuration options. Each bit of these input/output latches can be set or cleared using the SET [m].i and CLR [m].i instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O line has a pull-high option. Once a pull-high option is selected, the I/O line has a pull-high resistor connected, otherwise, there are none. Take note that a non-pull-high I/O line operating as an input will be in a floating state. Pin PA3 is pin-shared with the PFD signal. If the PFD configuration option is selected, the output signal on PA3, if setup as an output, will be the PFD signal generP u ll- H ig h O p tio n PA PA PA PA PA PA PB PC PD 7 0~P 3 /P 4 /T 5 /IN 6 /IN A2 FD MR T0 T1
ated by the timer/event counter overflow signal. If setup as an input then the pin will retain its input function. Once the PFD configuration option is selected, the PFD output signal is controlled by the PA3 data register. Writing a 1 to the PA3 data register will enable the PFD output function and writing 0 will force pin PA3 to remain at 0. The I/O functions of PA3 are shown below. I/O Mode PA3 Note: I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on)
The PFD frequency is the timer/event counter overflow frequency divided by 2.
PA6, PA5 and PA4 are pin-shared with the INT0, INT1 and TMR pins respectively. PB and PC can also be used as A/D converter inputs. The A/D function will be described later. There are two SPI interfaces which are shared with pins PD1~PD4, PD7 and PF0~PF2. The SPI function will be described later. There is a PWM function shared with pin PD0. If the PWM function is enabled, the PWM signal will appear on pin PD0 (if PD0 is setup as an output). Writing a 1 to the PD0 data register will enable the PWM output function and writing a 0 will force the PD0 to remain at 0. The I/O functions of PD0 are shown in the table. I/O Mode PD0 I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PWM) Logical Input O/P (PWM) PWM
It is recommended that unused or not bonded out I/O
V
DD
C o n tr o l B it D a ta B u s D CK S Q W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r Q
D a ta B it D Q CK S Q M U X PFDEN (P A 3 ) U X W a k e - u p o p tio n
W r ite D a ta R e g is te r
0 /A N 0 ~ P B 7 /A N 7 0 /A N 8 ~ P C 7 /A N 1 5 0 /P W M
PA3 (P D 0 o r P W M ) PFD M R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly )
IN T fo r P A 5 O n ly T M R fo r P A 4 O n ly
Input/Output Ports
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lines should be set as output pins using software instructions to minimise power consumption should they be inadvertently setup as floating inputs. Pulse Width Modulator - PWM The microcontroller provides a single channel (6+2) bit Pulse Width Modulator output shared with pin PD0. Its data register is known as PWM. The frequency source for the PWM counter comes from fSYS. The PWM register is an eight bit register. If the configuration option selects pin PD0 to be a PWM output, and if the pin is setup as an output by setting bit PDC.0 to 0, then writing 1 to the PD0 data register will enable the PWM output function. Writing a 0 will force the PD0 to stay at 0. A PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock periods. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which has the value of PWM.7~PWM.2. Group 2 is denoted by AC which has the value of PWM.1~PWM.0. In a PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) iThe modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency fSYS/64 PWM Cycle Frequency fSYS/256 PWM Cycle Duty [PWM]/256
fS
YS
/2
[P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0
YS
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4 M o d u la tio n c y c le 1 PW M
2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS
YS
2 5 /6 4 M o d u la tio n c y c le 3
2 6 /6 4 M o d u la tio n c y c le 0
PWM
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A/D Converter A 16 channel 8-bit resolution A/D converter is integrated within the microcontroller. The A/D reference voltage is VDD. The A/D converter contains several special registers, which are ADR, ADCR and ACSR. The ADR register is the A/D result register and is read-only. After an A/D conversion has completed, the ADR register is read to obtain the conversion result data. The EOCB flag will also be automatically cleared to indicate the end of conversion. The ADCR register is the A/D converter control register, which selects the analog channel, contains the start A/D conversion control bit and the end of A/D conversion flag. To initiate an A/D conversion, the analog channel is first selected and then the START bit is given a falling edge. When the conversion is complete, the EOCB bit will be cleared and an A/D converter interrupt is generated. The ACSR register selects the A/D clock source as well as selecting which pins are to be used as A/D inputs. Bits 0~3 of ADCR are used to select an analog input channel. There are a total of 16 channels to select. Bits 3~6 of ADSR are used to select which pins on Port B and Port C are setup as normal I/Os or A/D inputs. The EOCB bit in the ADCR registers, is end of A/D conversion flag. This bit can be monitored to check when the A/D conversion has completed. The START bit in the ADCR register is used to initiate A/D conversion process. Providing the START bit with a rising edge will reset and start the A/D conversion. When checking for the end of an A/D conversion, the START bit should remain at 0 and the EOCB bit monitored until it is cleared to 0 which indicates the end of conversion. Bit 7 of the ACSR register is used for testing purposes Bit No. 0~3 4~5 6 7 Label ACS0~ ACS3 3/4 EOCB START Analog channel selection Reserved bit Indicates end of A/D conversion (read only). (0 = end of A/D conversion) Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= Reset A/D converter and set EOCB to 1) ADCR (22H) Register Bit No. Label Function ADCS1,ADCS0 : Selects the A/D converter clock source 0, 0: fSYS/2 0, 1: fSYS/8 1, 0: Undefined 1, 1: Undefined (fWDT for test only) Unused bit, read as 0. Port B & Port C configuration selection. If PCR0, PCR1 and PCR2, PCR3 are all zero, the ADC circuit is power off to reduce power consumption For internal test only, read as 1. ACSR (23H) Register Rev. 1.00 18 December 20, 2006 Function only and should not be used. Bits 1 and bit 0 are used to select the A/D converter clock source. When the A/D conversion has completed, the A/D interrupt request flag is set. The EOCB bit is set to 1 automatically when the START bit is set to 1. Bit7 D7 Bit6 D6 Bit5 D5 Bit4 D4 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0
ADR (21H) Register ACS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ACS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ACS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ACS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Analog Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
0 1
ADCS0 ADCS1
2 3~6 7
3/4 PCR0~ PCR3 TEST
HT82J30R/HT82J30A
PCR3 PCR2 PCR1 PCR0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 AN0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 AN1 AN0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3 AN2 AN1 AN0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 AN3 AN2 AN1 AN0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 AN4 AN3 AN2 AN1 AN0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 AN5 AN4 AN3 AN2 AN1 AN0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PC7 PC6 PC5 PC4 PC3 PC2 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PC7 PC6 PC5 PC4 PC3 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PC7 PC6 PC5 PC4 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PC7 PC6 PC5 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PC7 PC6 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
M in im u m
o n e in s tr u c tio n c y c le n e e d e d
START EOCB A /D s a m p lin g tim e 3 2 tA D PC R3~PC R0 000B 100B A /D s a m p lin g tim e 3 2 tA D 100B 000B 1 . P B a n d P C s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n AC S3~ACS0 000B P o w e r-o n R eset R e s e t a n d S ta rt o f A /D c o n v e rte r 1 : D e fin e P B , P C c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D c lo c k m u s t b e fS
YS
010B
000B
d o n 't c a r e
R e s e t a n d S ta rt o f A /D c o n v e rte r E n d o f A /D c o n v e r s io n E n d o f A /D c o n v e r s io n 7 6 tA D A /D c o n v e r s io n tim e
7 6 tA D c o n v e r s io n tim e
YS
/2 o r fS
/8
A/D Conversion Timing
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December 20, 2006
HT82J30R/HT82J30A
Example: using EOC Polling Method to detect end of conversion. clr INTC mov a, 0010B mov ADCR,a mov a, 00000001B mov ACSR,a Start_conversion: clr .7 set ADCR.7 clr ADCR.7 Polling_EOC: sz ADCR.6 jmp polling_EOC mov a, ADR mov adr_buffer,a : : jmp start_conversion ; disable A/D interrupt in interrupt control register ; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select ; AN0 to be connected to the A/D converter ; setup the ACSR register to select fSYS/8 as the A/D clock
; reset A/D ; start A/D ; poll the ADCR register EOC bit to detect end of A/D conversion ; continue polling ; read conversion result from the high byte ADRH register ; save result to user defined register
; start next A/D conversion
Example: using Interrupt method to detect end of conversion. set INTC mov a, 0010B mov ADCR,a mov a, 00000001B mov ACSR,a : Start_conversion: clr ADCR.7 set ADCR.7 clr ADCR.7 : : EOC_service routine: mov a_buffer,a mov a,ADR mov adr_buffer,a clr .7 set ADCR.7 clr ADCR.7 mov a,a_buffer reti ; enable A/D interrupt in interrupt control register ; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select ; AN0 to be connected to the A/D converter ; setup the ACSR register to select fSYS/8 as the A/D clock
; reset A/D ; start A/D
; interrupt service routine ; save ACC to user defined register ; read conversion result from the high byte ADRH register ; save result to user defined register ; reset A/D ; start A/D ; restore ACC from temporary storage
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HT82J30R/HT82J30A
SPI Serial Interface There are two SPI interfaces, with each interface containing four basic signals and pins. These are SDI (serial data input), SDO (serial data output), SCK (serial clock) and SCS (slave select pin). Note that each of these pin names will be suffixed with either an A or B to denote which SCI interface is being used, however to minimise repetition, this will not be
SC S_A,SC S_B tC SC K_A,SC K_B
S_SK
tS
P IC K
tC
S_SK
S D I_ A , S D I_ B
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SD O _A,SD O _B
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D7 SBC R _A,SBC R _B D EFAU LT SBD R _A,SBD R _B D EFAU LT U CKS 0 D7
D6 M1 1 D6 U
D5 M0 1 D5 U
D4 SBEN 0 D4 U
D3 M LS 0 D3 U
D2 CSEN 0 D2 U
D1 W COL 0 D1 U
D0 TRF 0 D0 U SBCR : S E R IA L B U S
C O N T R O L R E G IS T E R SBDR : S E R IA L B U S
D A T A R E G IS T E R
N o te : "U " m e a n s u n c h a n g e d .
mentioned in the description. Two corresponding registers, SBCR and SBDR are unique to the serial interface and provide control, status, and data storage.
* SBCR_A, SBCR_B: Serial bus control register
Disable: SCK (SCK), SDI, SDO, SCS floating Bit3 (MLS) (R) MSB or LSB (1/0) shift first control bit Bit2 (CSEN) (R) serial bus selection signal enable/disable (SCS), when CSEN=0, SCSB is floating. Bit1 (WCOL) (R) this bit is set to 1 if data is written to the SBDR register (TXRX buffer) when data is transferred, writing will be ignored if data is written to SBDR (TXRX buffer) when data is transferred. Bit0 (TRF) (R) data transferred or data received used to generate an interrupt. Note: data reception is still in operation when the MCU enters the Power-down mode.
Bit7 (CKS) clock source selection: fSIO=fSYS/4, select as 0 Bit6 (M1), Bit5 (M0) master/slave mode and baud rate selection M1, M0: 00 (R) MASTER MODE, BAUD RATE= fSIO 01 (R) MASTER MODE, BAUD RATE= fSIO/4 10 (R) MASTER MODE, BAUD RATE= fSIO/16 11 (R) SLAVE MODE
* Bit4 (SBEN) (R) serial bus enable/disable (1/0)
* SBDR_A, SBDR_B: Serial bus data register
Enable: (SCS dependent on CSEN bit) Disable (R) enable: SCK, SDI, SDO, SCS= 0 (SCKB= 0) and waiting for writing data to SBDR (TXRX buffer) Master mode: write data to SBDR (TXRX buffer) start transmission/reception automatically Master mode: when the data has been transferred, set TRF Slave mode: when an SCK (and SCS dependent on CSEN) is received, data in the TXRX buffer is shifted-out and data on SDI is shifted-in.
Data written to SBDR (R) write data to the TXRX buffer only Data read from SBDR (R) read from SBDR only Operating Mode description: Master transmitter: clock transmission and data I/O started by writing to SBDR Master clock transmission initiated by writing to SBDR Slave transmitter: data I/O started by clock reception Slave receiver: data I/O started by clock reception
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HT82J30R/HT82J30A
Clock polarity= rising (SCK) or falling (SCK): 1 or 0 (mask option). Modes 1. 2. 3. 4. Master 5. 6. 7. 8. 9. 1. 2. 3. 4. Slave 5. 6. 7. 8. 9. Operations Select CKS and select M1, M0 = 00,01,10 Select CSEN, MLS (the same as the slave) Set SBEN Writing data to SBDR (R) data is stored in TXRX buffer (R) output SCK (and SCS) signals (R) go to step 5 (R) (SIO internal operation (R) data stored in TXRX buffer, and SDI data is shifted into TXRX buffer (R) data transferred, data in TXRX buffer is latched into SBDR) Check WCOL; WCOL= 1 (R) clear WCOL and go to step 4; WCOL= 0 (R) go to step 6 Check TRF or waiting for SBI (serial bus interrupt) Read data from SBDR Clear TRF Go to step 4 CKS dont care and select M1, M0= 11 Select CSEN, MLS (the same as the master) Set SBEN Writing data to SBDR (R) data is stored in TXRX buffer (R) waiting for master clock signal (and SCS): SCK (R) go to step 5 (R) (SIO internal operations (R) SCK (SCS) received (R) output data in TXRX buffer and SDI data is shifted into TXRX buffer (R) data transferred, data in TXRX buffer is latched into SBDR) Check WCOL; WCOL= 1 (R) clear WCOL, go to step 4; WCOL= 0 (R) go to step 6 Check TRF or wait for SBI (serial bus interrupt) Read data from SBDR Clear TRF Go to step 4 Operation of Serial Interface
WCOL: master/slave mode, set while writing to SBDR when data is transferring (transmitting or receiving) and this writing will then be ignored. WCOL function can be enabled/disabled by mask option. WCOL is set by SIO and cleared by users. Data transmission and reception are still working when the MCU enters the HALT mode. CPOL is used to select the clock polarity of SCK. It is a mask option. MLS: MSB or LSB first selection. CSEN: chip select function enable/disable, CSEN=1 (R) SCS signal function is active. Master should output SCS signal before SCL signal is set and slave data transferring should be disabled (or enabled) before (after) SCS signal is received. CSEN= 0, SCS signal is not needed, SCS pin (master and slave) should be floating. CSEN
has 2 options: CSEN mask option is used to enable/disable software CSEN function. If CSEN mask option is disabled, the software CSEN is always disabled. If CSEN mask option is enabled, software CSEN function can be used. SBEN= 1 (R) serial bus standby; SCS (CSEN= 1) = 1; SCS= floating (CSEN= 0); SDI= floating; SDO= 1; master SCK= output 1/0 (dependent on CPOL mask option), slave SCK= floating. SBEN= 0 (R) serial bus disabled; SCS=SDO=1, SDI=SCK= floating in master mode, SDI=SDO=SCK= floating, SCS=1 in slave mode. TRF is set by SIO and cleared by users. When data transfer (transmission and reception) is completed, TRF is set to generate SBI (serial bus interrupt).
Rev. 1.00
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HT82J30R/HT82J30A
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R SCS SCK SDI SDO SCK SBCR D e fa u lt SBDR D e fa u lt D7 CKS 0 D7 u D6 M1 1 D6 u D5 M0 1 D5 u D4 SBEN 0 D4 u D3 M LS 0 D3 u D2 CSEN 0 D2 u D1 WCOL 0 D1 u D0 TRF 0 D0 u D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 S B E N = C S E N = 1 a n d w r ite d a ta to S B D R ( if p u ll- h ig h e d )
N o te : "u " m e a n s u n c h a n g e d . D a ta B u s SBDR ( R e c e iv e d D a ta R e g is te r )
D7D6D5D4D3D2D1D0 M
U X
SDO
B u ffe r SBEN
SDO
M LS M U X M U X C0C1C2 In te r n a l B a u d R a te C lo c k SCK EN a n d , s ta rt C lo c k P o la r ity a n d , s ta rt SDI
TRF AND W C O L F la g
M a s te r o r S la v e SBEN In te r n a l B u s y F la g SBEN
W r ite S B D R
a n d , s ta rt EN
W r ite S B D R E n a b le /D is a b le W r ite S B D R
SCS
M a s te r o r S la v e SBEN CSEN W C O L:setb CSEN:enab 1 . m a s te r 2 . s la v e m SBEN :enab 1.W hen S 2.W hen S T R F 1 : d a ta C P O L 1 /0 : c y S IO c le a r e d b y u s e r s le /d is a b le c h ip s e le c tio n fu n c tio m o d e 1 /0 : w ith /w ith o u t S C S o u o d e 1 /0 : w ith /w ith o u t S C S in p u le /d is a b le s e r ia l b u s ( 0 : in itia liz B E N = 0 , a ll s ta tu s fla g s s h o u ld B E N = 0 , a ll S IO r e la te d fu n c tio tr a n s m itte d o r r e c e iv e d , 0 : d a ta lo c k p o la r ity r is in g /fa llin g e d g e n tp t e p in u t fu n c tio n c o n tr o l fu n c tio a ll s ta tu s fla g b e in itia liz e d n p in s s h o u ld s is tr a n s m ittin g : m a s k o p tio n
n s) ta y a t flo a tin g s ta te o r s till n o t r e c e iv e d
Rev. 1.00
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December 20, 2006
HT82J30R/HT82J30A
Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as when changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) has to remain in its origi-
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
V 3 .0 V 2 .2 V
LVR
nal state for longer than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
* The LVR uses an OR function with the external RES
0 .9 V
Note:
VOPR is the voltage range for proper chip operation at 4MHz system clock.
signal to perform a chip reset.
V 5 .5 V
DD
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before starting normal operation. *2: Since a low voltage has to be maintained in its original state for longer than 1ms, therefore a 1ms delay enters the reset mode.
Rev. 1.00
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December 20, 2006
HT82J30R/HT82J30A
Options The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper system functioning. Items 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Lock or unlock (1/0) PA0~PA7 wake-up enable or disable (1/0) options WDT clock source (fS) : WDTOSC/ fTID (0/1) CLR WDT instruction(s): one or two clear WDT instruction(s) (1/0) WDT enable or disable (0/1) PA pull-high enable or disable (1/0) PB pull-high enable or disable (1/0) by nibble PC pull-high enable or disable (1/0) by nibble PD pull-high enable or disable (1/0) by nibble PF pull-high enable or disable (1/0) by nibble PWM enable or disable PFD enable or disable System oscillators 0/1: RC/crystal Low voltage reset: Enable or disable LVR voltage: 3.0V/3.8V (0/1) SIO_A (Serial Interface) enable or disable (default disable) SIO_A_ CPOL: Clock polarity 1/0 : clock polarity rising or falling edge (default falling edge) SIO_A_WCOL: Enable or disable (default disable) SIO_A_CSEN: Enable or disable, CSEN mask option is used to enable or disable software CSEN function (default disable) PD4, PB2, PB3, PD7 CMOS or NMOS output (default CMOS) SIO_B (Serial Interface) enable or disable (default disable) SIO_ B_CPOL: Clock polarity 1/0: clock polarity rising/falling edge (default falling edge) SIO_B_WCOL: Enable or disable (default disable) SIO_B_CSEN: Enable or disable, CSEN mask option is used to enable or disable software CSEN function (default disable) Options
Rev. 1.00
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December 20, 2006
HT82J30R/HT82J30A
Application Circuits
V
DD
0 .0 1 m F * 100kW 0 .1 m F
VDD RES
PA0~PA2 P A 3 /P F D P A 4 /T M R P A 5 /IN T 0 P A 6 /IN T 1 R PA7 P B 0 /A N 0 P B 7 /A N 7 ~ P C 0 /A N 8 P C 7 /A N 1 5 ~ P D 0 /P W M PF0~PF2 V
DD OSC
10kW
0 .1 m F * VSS
470pF C1
OSC1
R C S y s te m O s c illa to r 30kW OSC2 N M O S o p e n d r a in OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r
OSC C ir c u it S e e R ig h t S id e
OSC1 OSC2
C2 R1
OSC2 OSC
H T 8 2 J 3 0 R /H T 8 2 J 3 0 A
C ir c u it
Note:
The resistance and capacitance for the reset circuit should be designed to ensure that VDD is stable and remains within a valid range of the operating voltage before bringing RES high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator (3 pins) 4MHz Resonator (2 pins) 3.58MHz Crystal 3.58MHz Resonator (2 pins) 2MHz Crystal & Resonator (2 pins) 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator C1, C2 0pF 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Rev. 1.00
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December 20, 2006
HT82J30R/HT82J30A
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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December 20, 2006
HT82J30R/HT82J30A
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.00
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December 20, 2006
HT82J30R/HT82J30A
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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HT82J30R/HT82J30A
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
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December 20, 2006
HT82J30R/HT82J30A
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Rev. 1.00
31
December 20, 2006
HT82J30R/HT82J30A
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
Rev. 1.00
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HT82J30R/HT82J30A
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Rev. 1.00
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HT82J30R/HT82J30A
MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
Rev. 1.00
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HT82J30R/HT82J30A
RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
Rev. 1.00
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HT82J30R/HT82J30A
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rev. 1.00
36
December 20, 2006
HT82J30R/HT82J30A
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
37
December 20, 2006
HT82J30R/HT82J30A
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
38
December 20, 2006
HT82J30R/HT82J30A
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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HT82J30R/HT82J30A
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
40
December 20, 2006
HT82J30R/HT82J30A
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.00
41
December 20, 2006
HT82J30R/HT82J30A
Package Information
28-pin SKDIP (300mil) Outline Dimensions
A 28 B 1 15 14
H C D E F G
a
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 1375 278 125 125 16 50 3/4 295 330 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1395 298 135 145 20 70 3/4 315 375 15
Rev. 1.00
42
December 20, 2006
HT82J30R/HT82J30A
28-pin SOP (300mil) Outline Dimensions
28 A
15 B
1
14
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10
Rev. 1.00
43
December 20, 2006
HT82J30R/HT82J30A
44-pin QFP (1010) Outline Dimensions
C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H
Symbol A B C D E F G H I J K L a
Dimensions in mm Min. 13 9.9 13 9.9 3/4 3/4 1.9 3/4 0.25 0.73 0.1 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.8 0.3 3/4 3/4 3/4 3/4 3/4 0.1 3/4 Max. 13.4 10.1 13.4 10.1 3/4 3/4 2.2 2.7 0.5 0.93 0.2 3/4 7
Rev. 1.00
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HT82J30R/HT82J30A
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 24.8+0.3 -0.2 30.20.2
Rev. 1.00
45
December 20, 2006
HT82J30R/HT82J30A
Carrier Tape Dimensions
D
E F
P0
P1
t
W C
B0
D1
P
K0 A0
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 240.3 120.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 40.1 20.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3
Rev. 1.00
46
December 20, 2006
HT82J30R/HT82J30A
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com
Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
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December 20, 2006

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